Processor, system, and method for dynamic cache allocation
US12360900B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 28, 2024 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Feb 28, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a processing core configured to process each of a plurality of requests by accessing a corresponding one of a first memory and a second memory, a latency monitor configured to generate first latency information and second latency information, the first latency information comprising a first access latency to the first memory, and the second latency information comprising a second access latency to the second memory, a plurality of cache ways divided into a first partition and a second partition, and a decision engine configured to allocate each of the plurality of cache ways to one of the first partition and the second partition, based on the first latency information and the second latency information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.