Display panel and display device
US12361881B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2024 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Jan 31, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display panel comprises a display portion comprising sub-pixel rows and a gate driver circuit comprising gate driver units in cascade. Each sub-pixel row comprises sub-pixel units, and a pixel circuit comprising a switching transistor, a first reset transistor and a second reset transistor is provided in each sub-pixel unit. Each gate driver unit comprises first and second signal output terminals. Agate of the switching transistor in a b-th row is connected to the second signal output terminal of the gate driver unit at an a-th stage, a gate of the first reset transistor in the b-th row is connected to the first signal output terminal of the gate driver unit at a b-th stage, and a gate of the second reset transistor in the b-th row is connected to the first signal output terminal of the gate driver unit at a c-th stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.