Semiconductor memory device
US12362023B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2022 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Mar 10, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device performs: an erase voltage supply operation that applies an erase voltage to a first wiring; a first erase verify operation that applies a read pass voltage to a first conductive layer, and applies an erase verify voltage to a second conductive layer after performing the erase voltage supply operation; and a second erase verify operation that applies the erase verify voltage to the first conductive layer, and applies the read pass voltage to the second conductive layer after performing the first erase verify operation. The erase voltage increases by a first offset voltage in each erase loop from a first erase loop to an a-th erase loop, and the erase voltage increases by a second offset voltage in each erase loop from an a+1-th erase loop to a b-th erase loop. The second offset voltage is larger than the first offset voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.