Anti-fuse address decoding circuit, operation method, and memory
US12362025B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Feb 9, 2023 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Oct 22, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5252
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An anti-fuse address decoding circuit includes: a pre-decoding circuit, configured to decode a programming address of an anti-fuse memory array and output a programming address pre-decoded signal; a level shift circuit, coupled to the pre-decoding circuit, and configured to boost the programming address pre-decoded signal and output a boosted signal; and a programming address decoding circuit, configured to receive the boosted signal, decode the boosted signal and output a programming address signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.