Memory test circuit, memory chip, and testing method of memory chip
US12362028B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2023 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Sep 21, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory test circuit is provided. The memory test circuit is disposed in a memory chip and electrically coupled to a memory macro of the memory chip. A high speed clock receives an input signal and an external clock signal. The input signal includes a plurality of test bits. A finite state machine controller provides a pattern type. A pattern generator generates and provides a test signal to at least one memory cell of the memory chip to write the test signal to the at least one memory cell based on the pattern type and the external clock signal. A test frequency of the test signal is determined based on the high speed clock. An output comparator outputs a comparison signal based on a difference between the test signal and a readout signal corresponding to the test signal read from the at least one memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.