MIM structure
US12362271B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2021 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Jan 23, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/042
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of manufacturing a three dimensional (3D) metal-insulator-metal (MIM) capacitor in the back end of line, which can provide large and tunable capacitance values and meanwhile, does not interfere with the existing BEOL fabrication process. In one embodiment, a method for fabricating a semiconductor device includes: forming a first conductive feature on a semiconductor substrate; forming a second conductive feature on the semiconductor substrate; forming a first via structure over the first conductive feature; forming a first metallization structure over the first via structure, wherein the first metallization structure is conductively coupled to the first conductive feature through the first via structure; forming a conductive etch stop structure on the first metallization structure; forming a first via hole above the conductive etch stop structure and a second via hole above the second conductive feature, wherein the first via hole exposes the conductive etch stop structure and the second via hole is deeper than the first via hole; and forming a capacitor in the second via hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.