Digital-to-analog converter (DAC) with dynamic stacked cascode switches
US12362761B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2023 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Jan 19, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/742
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Certain aspects of the present disclosure generally relate to a digital-to-analog converter (DAC) circuit implemented with a dynamic stacked transistor architecture. The DAC circuit generally includes a first current-steering transistor and a second current-steering transistor. The DAC circuit may also include: a first stacked transistor coupled between the first current-steering transistor and a first output of the DAC circuit; a first switch coupled between a gate of the first stacked transistor and a bias voltage node; a second switch coupled between the gate of the first stacked transistor and a voltage rail; a second stacked transistor coupled between the second current-steering transistor and a second output of the DAC circuit; a third switch coupled between a gate of the second stacked transistor and the bias voltage node; and a fourth switch coupled between the gate of the second stacked transistor and the voltage rail.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.