Memory system, memory controller, and method of controlling non-volatile memory
US12362768B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2024 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Feb 12, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1575
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory system includes a non-volatile memory and a memory controller. The memory stores data encoded with an error correction code for correcting errors of n (n is 3 or more) bits or less. The controller estimates the number of error bits by using syndromes calculated from a received word. When the number of error bits is two or three, the controller executes variable transformation on a variable of an error locator polynomial corresponding to the number of error bits with a first value or a second value based on the syndromes. The controller also executes, with the first/second values, calculation of roots of a transformed polynomial obtained by converting the error locator polynomial. The controller obtains roots of the error locator polynomial by variable inverse transformation on the roots of the transformed polynomial and corrects the error of the error locations corresponding to the obtained roots.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.