Mechanisms to reduce the worst-case latency for ultra-low latency applications
US12363778B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2021 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Nov 15, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W84/12
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
This disclosure describes systems, methods, and devices related to latency reduction. The device may set up a plurality of links between an access point (AP) multi-link device (MLD) and a non-AP MLD. The device may encode a frame for transmission on a first link of the plurality of links between a first AP of the AP MLD and a first STA of the non-AP MLD. The device may identify an indication received at a second STA of the non-AP MLD using an interference mitigation signal. The device may cause to stop the transmission of the frame on the first link based on the indication. The device may identify a second frame on the first link received from the first AP. The device may cause to resume the transmission of the first frame on the first link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.