Three-dimensional memory device with capacitors and vertical word-line
US12363884B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 24, 2022 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Dec 8, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
Abstract
A semiconductor structure includes a substrate; at least one layer of memory structure formed on the substrate, in which each layer of memory structure comprises a bit line structure and a plurality of capacitor structures symmetrically distributed on both sides of the bit line structure, the plurality of capacitor structures and the bit line structure extend in a first direction parallel to the substrate surface; a plurality of word line structures formed in the at least one layer of memory structure, which pass through the at least one layer of memory structure and extend in a second direction perpendicular to the substrate surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.