Hybrid transistor and memory cell
US12363914B2 · kind B2 · utility
0Cited by
1References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2022 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Feb 13, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hybrid switch and memory cell includes a transistor device that has an atomically-thin semiconductor material channel, source/drain electrodes, and gate dielectric. The cell includes a resistive-random-access-memory having a thin conductive edge and a 2D insulator layer over the thin conductive edge, wherein the 2D insulator layer extends over the semiconductor channel and serves as the gate dielectric in the transistor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.