Semiconductor device and power conversion device
US12363943B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2021 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Jun 10, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D12/441
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
To mitigate adverse effects on a surface electrode of a semiconductor device. The semiconductor device includes: a first well region formed in a surface layer of an upper surface of a drift layer; a gate electrode; a second well region surrounding the first well region as seen in plan view; and a gate portion covering an interlayer insulation film and the gate electrode exposed from the interlayer insulation film. An outside edge portion of the gate electrode is farther from the first well region than an outside edge portion of the gate portion and closer to the first well region than an outside edge portion of the second well region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.