Display panel and display device with cathode suppression layer in a spacer
US12364107B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Aug 4, 2021 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Sep 26, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/65
Abstract
A display panel and a display device are provided. The display panel having a first display region includes a base, a pixel definition layer, and first spacers. At least one of the first spacers is provided with a via hole, and a first cathode suppression layer is disposed in the via hole. The first cathode suppression layer causes no cathode layer deposited in the via holes of the first spacers. In this way, the light transmittance of each of the first spacers in the first display region is increased, thereby increasing the light transmittance of the first display region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.