Array substrate and display apparatus
US12366781B2 · kind B2 · utility
0Cited by
5References
18Claims
0Family size
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Key dates
| Filing date | Aug 11, 2021 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | Jun 10, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2202/16
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate includes sub-pixels arranged in an array, scan lines, and data lines on a base substrate, with any one of the sub-pixels including a pixel electrode and a switch transistor; wherein the pixel electrode is connected to a drain electrode of the switch transistor, a gate electrode of the switch transistor is connected to one of the scan lines, a source electrode of the switch transistor is connected to one of the data lines; and an active layer of the switch transistor of the sub-pixel is located between the pixel electrode of the sub-pixel and the data line connected to the sub-pixel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.