Circuit for combined down sampling and correction of image data
US12367545B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2023 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | Sep 5, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N23/88
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A foveated down sampling and correction (FDS-C) circuit for combined down sampling and correction of chromatic aberrations in images. The FDS-C circuit performs down sampling and interpolation of pixel values of a first subset of pixels of a color in a raw image using down sampling scale factors and first interpolation coefficients to generate first corrected pixel values for pixels of the color in a first corrected version of the raw image. The FDS-C circuit further performs interpolation of pixel values of a second subset of the pixels in the first corrected version using second interpolation coefficients to generate second corrected pixel values for pixels of the color in a second corrected version of the raw image. Pixels in the first subset are arranged in a first direction, pixels in the second subset are arranged in a second direction, and the down sampling scale factors vary along the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.