Pseudo-differential de-glitch sense amplifier
US12367927B2 · kind B2 · utility
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27References
21Claims
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Key dates
| Filing date | Jan 31, 2023 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | Jan 6, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory is provided with a pseudo-differential sense amplifier for single-endedly sensing a first read bit line from a first bank of bitcells. The sense amplifier compares a voltage of the first read bit line to a voltage of a pre-charged second read bit line from a second bank of bitcells to make a bit decision for a read operation through the first read bit line to the first bank of bitcells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.