Semiconductor test sample and manufacturing method thereof
US12368051B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | Jul 22, 2021 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | Jul 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor test sample includes: providing a product to be analyzed, the product comprises a conductive interconnection layer and a semiconductor doped region located below the conductive interconnection layer; selectively removing a conductive material from the conductive interconnection layer, replacing the conductive material with a non-conductive material and replacing the conductive interconnection layer with an insulating sacrificial layer; and taking the product including both the insulating sacrificial layer and the semiconductor doped region as a semiconductor test sample.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.