D flip-flop having multiplexer function
US12368434B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2023 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | Apr 12, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a D flip-flop having a multiplexer function, including: a first transmission gate whose data input end is configured to receive a first data signal and whose clock input end is configured to receive a first clock signal; a second transmission gate whose data input end is configured to receive a second data signal and whose clock input end is configured to receive a second clock signal; an inverted latch unit whose data input end is connected to an output end of the first transmission gate and an output end of the second transmission gate and whose clock input end is configured to receive a third clock signal; and an inverter whose input end is connected to an output end of the inverted latch unit and whose output end provides an output of the D flip-flop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.