Semiconductor structure and manufacturing method thereof
US12369295B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2022 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | Jan 27, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
Abstract
The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, where the base is provided with an array region and a peripheral region, the array region is provided with vertical transistor structures, the vertical transistor structures are arranged in an array in the array region, and the peripheral region surrounds the array region; a first gate layer surrounding the vertical transistor structure and extending along a first direction; a second gate layer surrounding the vertical transistor structure and extending along the first direction, where the second gate layer and the first gate layer surround a same vertical transistor structure, are disposed at intervals, and both extend to the peripheral region; and an electrical connection structure located in the peripheral region and electrically connected to the first gate layer and the second gate layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.