Semiconductor structure and manufacturing method thereof
US12369297B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2022 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | Feb 22, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base including a first region and a second region, where a plurality of active pillars are arranged at intervals in the base located in the first region; forming a first dielectric layer on the base, where the first dielectric layer covers the plurality of active pillars; forming a first mask layer with a first mask pattern on the first dielectric layer; forming a second mask layer with a second mask pattern on the first mask layer; forming a third mask layer with a third mask opening, where the third mask opening is used to expose the first region; and removing part of the first dielectric layer by using the first mask layer, the second mask layer, and the third mask layer as a mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.