Microelectronic devices with isolation trenches in upper portions of tiered stacks, and related methods
US12369333B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Mar 4, 2024 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | Mar 4, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/016
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for forming microelectronic devices include forming lower and upper stack structures, each comprising vertically alternating sequences of insulative and other structures arranged in tiers. Lower and upper pillar structures are formed to extend through the lower and upper stack structures, respectively. An opening is formed through the upper stack structure, and at least a portion of the other structures of the upper stack are replaced by (e.g., chemically converted into) conductive structures, which may be configured as select gate structures. Subsequently, a slit is formed, extending through both the upper and lower stack structures, and at least a portion of the other structures of the lower stack structure are replaced by a conductive material within a liner to form additional conductive structures, which may be configured as access lines (e.g., word lines). Microelectronic devices and structures and related electronic systems are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.