Array substrate having an active layer structure with two layers in parallel and display panel having an active layer structure with two layers in parallel
US12369401B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2022 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | Nov 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/421
Abstract
Embodiments of the present disclosure provide an array substrate and a display panel. The array substrate includes a first active layer, a gate electrode, a gate insulating layer, a second active layer, and a source/drain metal layer. The first active layer is connected in parallel with the second active layer through a conductor layer. Through an active layer structure with two layers in parallel, an on-state current and mobility of equivalent carriers of a device are effectively improved, and a comprehensive performance of the device is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.