Method to manage periodic dram refresh and maintenance scheduling for predictable dram data access
US12373107B2 · kind B2 · utility
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22Claims
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Key dates
| Filing date | Dec 13, 2023 |
| Grant date | Jul 29, 2025 |
| Priority date | — |
| Expiry date | Jan 23, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When reading and writing DRAM (dynamic random-access memory), the latency and bandwidth is often unpredictable with large variations. One reason is because all the DRAM memory banks require periodic refreshes and maintenance cycles that interrupt these accesses. DRAM refresh and maintenance cycles are synchronized with the read/write accesses in a mutually exclusive manner, hence, preventing the accesses from being interfered with by a refresh or maintenance cycle resulting in predictable latency and bandwidth performance during read/write operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.