Spliced display screen reducing hashrate of inner processing algorithm
US12373154B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 31, 2023 |
| Grant date | Jul 29, 2025 |
| Priority date | — |
| Expiry date | Jul 31, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a spliced display screen. The spliced display screen includes a plurality of display screen modules, a plurality of control modules, and a communication bus; an image processing algorithm is configured in each control module; the each of the plurality of control modules is configured to receive video information and send an edge signal supplement request to other control modules; determine whether the communication bus is occupied by the each of the plurality of control modules; determine the each of the plurality of control modules as a master control module and other control modules as slave control modules; read at least part of edge information via the communication bus; and perform imaging processing on the received video information and multiple pieces of the at least part of edge information to generate image sub-information; and the plurality of display screen modules are configured to display received image sub-information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.