Register fault detector
US12373295B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2021 |
| Grant date | Jul 29, 2025 |
| Priority date | — |
| Expiry date | Nov 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault detector has a processor configured to receive, during a register write event, first data that are to be stored on a first register; determine a first encoded value from the first data using an encoding operation; receive second data from the first register from one or more bit locations on which the first data were to be stored; determine a second encoded value from the second data using the encoding operation; and compare the first encoded value and the second encoded value. If the first encoded value is the same as the second encoded value, the fault detector operates according to a first operational mode; and if the first encoded value is different from the second encoded value, the fault detector operates according to a second operational mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.