Systems and methods for multi-bit memory with embedded logic
US12373624B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2023 |
| Grant date | Jul 29, 2025 |
| Priority date | — |
| Expiry date | Jul 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0372
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and method are provided that include a standard cell with multiple input and output storage elements, such as flip flops, latches, etc., with some combination logic interconnected between them. In embodiments, the slave latches on input flip flops are replaced with a fewer number latches at a downstream node(s) of the combination logic resulting in improved performance, area and power, while maintaining functionality at the interface pins of the standard cell. The process of inferring such a standard cell from a behavioral description, such as RTL, of a design or remapping equivalent sub-circuits from a netlist to such a standard cell is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.