Low power phase interpolator with duty cycle correction
US12375073B1 · kind B1 · utility
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4References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 14, 2023 |
| Grant date | Jul 29, 2025 |
| Priority date | — |
| Expiry date | Aug 14, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In part, the disclosure relates to a source generating four input clock signals; a phase interpolator (PI) circuit that includes four PI quadrant circuits and a PI bias control circuit, wherein each PI quadrant circuit is configured to: receive, via the source, an input clock signal of the four input clock signals, and generate, based on the input clock signal, a pair of intermediate output clock signals of complementary phases; and a current mode logic (CML) to complementary metal-oxide-semiconductor (CMOS) converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.