Three level switching converter and control
US12376211B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2023 |
| Grant date | Jul 29, 2025 |
| Priority date | — |
| Expiry date | Nov 29, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05B45/335
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A circuit includes first, second third, and fourth transistors coupled in series, and a control circuit coupled to the first, second, third, and fourth transistors. The control circuit includes a clock generator, a current sense circuit, and a zero current differentiation zone (ZC_DF) circuit. The clock generator is configured to generate first and second clocks. The second clock is in quadrature with the first clock. The current sense circuit is configured to sense a current flowing through the first transistor. The ZC_DF circuit is configured to define a ZC_DF interval starting at an edge of the second clock and ending at turn-on of the fourth transistor. The control circuit is configured to operate the first, second, third, and fourth transistors in a discontinuous conduction mode (DCM), and, in DCM, turn off the first transistor during the ZC_DF interval responsive to the current flowing through the first transistor being negative.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.