Semiconductor structure, method for manufacturing same
US12376283B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2022 |
| Grant date | Jul 29, 2025 |
| Priority date | — |
| Expiry date | Jan 19, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor structure includes the following operations. A substrate is provided, and is etched to form first isolation trenches in a cell region and a second isolation trench in a peripheral region. A first isolation dielectric layer is filled in each of the first isolation trenches and an isolation structure is formed in the second isolation trench. A patterned mask layer is formed on surfaces of the cell region and the peripheral region. The substrate and the first isolation dielectric layer are etched based on the patterned mask layer to form the third isolation trenches extending along a second direction. The third and first isolation trenches isolate multiple active pillars. The active pillar includes a first connecting end, a second connecting end and a channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.