Memory device
US12376285B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2022 |
| Grant date | Jul 29, 2025 |
| Priority date | — |
| Expiry date | Feb 2, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/83
Abstract
A memory device is provided. The memory device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a first source/drain at one end of the fin structure, and a second source/drain at the other end of the fin structure, wherein the gate structure includes a trap layer, a blocking layer, and a gate electrode layer sequentially stacked on the fin structure, the first source/drain is doped with or has incorporated therein dopants of a first conductivity-type, and the second source/drain is doped with or has incorporated therein dopants of a second conductivity-type dopants that are different from the dopants of the first conductivity-type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.