Semiconductor memory device including a cyclic redundancy check engine and memory system including the same
US12379855B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2024 |
| Grant date | Aug 5, 2025 |
| Priority date | — |
| Expiry date | Feb 27, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/07
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.