Improving computing efficiency of a processor by optimizing a computational size of each computing core in the processor
US12380057B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2024 |
| Grant date | Aug 5, 2025 |
| Priority date | — |
| Expiry date | Sep 25, 2044 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for improving computing efficiency of a processor by optimizing a computational size of each computing core in the processor are provided. The techniques include obtaining a configuration space for a target parameter; obtaining a computational time model of the processor, the computational time model is a function of the target parameter and a number of computing cores of the processor; traversing the target parameter in the configuration space, and calculating, based on the computational time model, a computational time corresponding to the target parameter that is selected; in response to the target parameter being a k-th parameter with a minimum computational time, determining the target parameter as the k-th parameter; and improving the computing efficiency of the processor by configuring the computational size of each computing core in the processor based on the k-th parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.