Layout design method and method of manufacturing integrated circuit device using the same
US12380266B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Sep 21, 2023 |
| Grant date | Aug 5, 2025 |
| Priority date | — |
| Expiry date | Apr 25, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a layout design method including designing a preliminary layout including a source/drain contact pattern of an integrated circuit device, designing a first layout including a cut pattern for cutting the source/drain contact pattern, designing a second layout configured by excluding a pattern overlapping the pattern of the first layout from the preliminary layout, and correcting the preliminary layout by reflecting an etch skew based on at least one parameter of the second layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.