Method of manufacturing an interconnection structure for a semiconductor device having a spacer separating first and second conductive lines
US12381116B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2022 |
| Grant date | Aug 5, 2025 |
| Priority date | — |
| Expiry date | Nov 17, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53252
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an interconnection structure (10) for a semiconductor device is disclosed, wherein a first conductive layer is etched to form a set of third conductive lines (113) above a first and second conductive line (101, 108). At least one of the third conductive lines comprises a contacting portion forming a first via connection (114) to the second conductive line. The method further comprises forming spacers (115) on side walls of the set of third conductive lines, and forming, between two neighboring spacers, a via hole (116) extending to the underlying first conductive line. A second conductive layer is deposited, filling the via hole to form a second via connection (118) and forming a set of fourth conductive lines (119) extending between the spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.