Amplification system having power amplifier memory correction and/or current collapse correction
US12381517B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2022 |
| Grant date | Aug 5, 2025 |
| Priority date | — |
| Expiry date | Feb 1, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/451
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Amplification system having power amplifier memory correction and/or current collapse correction. In some embodiments, a power amplification system can include a power amplifier including an amplifying transistor configured to receive an input signal and provide an amplified signal, and a monitoring system configured to monitor one or more of a supply current for the amplifying transistor, an injection voltage point of the amplifying transistor, forward power at an output of the amplifying transistor, and temperature of the amplifying transistor. The power amplification system can further include a control system configured to obtain monitored information, and based on the information, generate a control signal for correcting either or both of a memory effect of the amplifying transistor and a current collapse effect of the amplifying transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.