Circuits and methods for accessing signals in integrated circuits
US12381561B2 · kind B2 · utility
0Cited by
5References
20Claims
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Assignee
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Key dates
| Filing date | Nov 13, 2021 |
| Grant date | Aug 5, 2025 |
| Priority date | — |
| Expiry date | Dec 6, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/343
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a monitored circuit and a signal analyzer circuit. The signal analyzer circuit includes a logic circuit that determines if a condition signal satisfies a condition to generate an output signal. A first-in-first-out (FIFO) buffer circuit stores opportunistic data indicated by a monitored signal received from the monitored circuit in response to the output signal indicating if the condition signal satisfies the condition. A communication channel transmits the opportunistic data stored in the FIFO buffer circuit outside the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.