2T0C semiconductor structure

US12382624B2 · kind B2 · utility

Assignee

• CHANGXIN MEMORY TECHNOLOGIES, INC. · CN

Inventors

• Youming Liu · Longbeilingcun, CN
• Deyuan Xiao · Shanghai, CN
• Xingsong SU · Hefei, CN

Key dates

• Filing date: Aug 15, 2022
• Grant date: Aug 5, 2025
• Expiry date: Jan 29, 2044

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B99/22

Abstract

Embodiments provide a semiconductor structure. The semiconductor structure includes a substrate, a dielectric layer arranged on the substrate, and a plurality of memory cell layers. The plurality of memory cell layers are spaced in the dielectric layer along a first direction, and projections of any adjacent two of the plurality of memory cell layers on the substrate are overlapped. Each of the plurality of memory cell layers includes a plurality of memory cells spaced along a second direction. According to the embodiments, the plurality of memory cell layers are spaced in the dielectric layer along a direction perpendicular to the substrate, and each of the plurality of memory cell layers has a plurality of memory cells therein; and a source, a channel and a drain in each of the plurality of memory cells are arranged along a direction parallel to the substrate.