Semiconductor device and forming method thereof
US12382649B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 26, 2021 |
| Grant date | Aug 5, 2025 |
| Priority date | — |
| Expiry date | Mar 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a gate structure over a substrate; forming a first gate spacer and a second gate spacer on opposite sidewalls of the gate structure, respectively; implanting a first dopant of a first conductivity type into the substrate form a lightly doped source region adjacent to the first gate spacer, and a lightly doped drain region adjacent to the second gate spacer; forming a patterned mask over a first portion of the lightly doped drain region, while leaving a second portion of the lightly doped drain region exposed; and with the patterned mask in place, implanting a second dopant of the first conductivity type into the substrate, resulting in converting the second portion of the lightly doped drain region into a drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.