Plasma-based barrier layer removal method for increasing peak transconductance while maintaining on-state resistance and related devices
US12382699B2 · kind B2 · utility
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28Claims
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Key dates
| Filing date | Jun 7, 2022 |
| Grant date | Aug 5, 2025 |
| Priority date | — |
| Expiry date | Jan 2, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor device includes a semiconductor structure comprising a channel layer and a barrier layer; source and drain contacts on the semiconductor structure; and a gate on the semiconductor structure between the source and drain contacts. A first portion of the barrier layer extending between the source or drain contact and the gate has a first thickness, a second portion of the barrier layer between the gate and the channel layer has a second thickness, and the first thickness is about 1.5 times to 4 times greater than the second thickness. Related methods of fabrication using a looped recess process are also discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.