Computer system with instruction pre-sending
US12386533B2 · kind B2 · utility
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7References
27Claims
0Family size
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Key dates
| Filing date | May 3, 2023 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Jun 3, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer architecture provides a pre-sending of memory blocks from a lower level memory hierarchy component to a higher level memory hierarchy component using a table linking a set of memory blocks holding instructions that are executed in different fragments of a program. The table is used to pre-send memory blocks to the higher level memory hierarchy component in anticipation of their use by a processor executing the program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.