Buffer management apparatus that uses pure hardware to manage buffer blocks configured in storage medium and associated buffer management method
US12386548B2 · kind B2 · utility
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2References
18Claims
0Family size
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Key dates
| Filing date | Jun 17, 2023 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Jun 17, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A buffer management apparatus includes a plurality of registers and a buffer block management circuit. The buffer block management circuit is used to communicate with software through the plurality of registers, and utilize pure hardware to manage a plurality of buffer blocks configured in a storage medium, for allowing the software to perform data access upon the plurality of buffer blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.