Memory array structure with dynamic differential-reference based readout scheme for computing-in-memory applications, dynamic differential-reference time-to-digital converter for computing-in-memory applications and computing method thereof
US12386592B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2022 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Jun 15, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic differential-reference time-to-digital converter for computing-in-memory applications is controlled by a bias reference and a predetermined setting parameter, and includes a configurable main-reference selector and a plurality of time-to-digital converters. The configurable main-reference selector is configured to receive a plurality of edge-output signals, select one of the edge-output signals as a main reference and select others of the edge-output signals as a plurality of edge selected signals according to the predetermined setting parameter. One of the time-to-digital converters is configured to compare the bias reference with the main reference to output a bias multiplication-and-accumulation value, and others of the time-to-digital converters are configured to compare the main reference with the edge selected signals to output a plurality of differential multiplication-and-accumulation values. The bias multiplication-and-accumulation value and the differential multiplication-and-accumulation values are dynamically adjusted according to the bias reference and the predetermined setting parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.