Decompilation apparatus and recompilation system for a processor architecture
US12386603B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2023 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Oct 26, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A decompilation apparatus includes a matcher that divides captured first program code for a processor of a first processor architecture into a sequence of code sections based on a predetermined set of at least partially parameterized code patterns, wherein the first program code implements a program logic and has been generated by compiling a computer program defined in a high-level language by a compiler, and the matcher captures for each code section specific parameter values for each parameter of a corresponding parameterized code pattern and assigns to each code section a terminal symbol of an intermediate language; and a parser that reduces a sequence of terminal symbols assigned to the sequence of code sections to non-terminal symbols of the intermediate language, wherein a totality of the non-terminal symbols generated by the parser by reduction describes the program logic of the computer program in the intermediate language.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.