Method of supporting persistence and computing device
US12386657B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 18, 2022 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Nov 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor of the computing device includes a plurality of cores and executes one or more instructions stored in a memory module including a non-volatile memory, thereby performing a stop procedure upon a power failure and performing a go procedure upon power recovery. In the stop procedure, the processor accesses process control blocks of processes being run, scheduling each process to a run queue of a corresponding first core among first cores included in the cores, removes the scheduled process from the run queue and makes the removed process wait in a waiting queue, executes an idle task, and stops a device included in the computing device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.