Patent · US Active

Processor trace with suppression of periodic timing packets for low density trace sections

US12386726B2 · kind B2 · utility

0Cited by

1References

15Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Markus T. Metzger · Ulm, DE
Beeman C. Strong · Portland, US

Key dates

Filing date	Dec 15, 2021
Grant date	Aug 12, 2025
Priority date	—
Expiry date	Sep 24, 2043

Classification

Technology area (CPC G)Physics
CPC primaryG06F2201/865
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An embodiment of an integrated circuit may comprise a processor and circuitry coupled to the processor to generate non-timing packets associated with a trace of an execution of code on the processor, generate timing packets associated with the trace of the execution of the code on the processor, wherein the timing packets include at least a full timestamp timing packet and a periodic timing packet, identify a low density section of the trace of the execution of the code on the processor, and suppress generation of periodic timing packets during the identified low density section of the trace of the execution of the code on the processor. Other embodiments are disclosed and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.