Selective fill for logical control over hardware multilevel memory
US12386748B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Mar 31, 2022 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Mar 12, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a multilevel memory such as a two level memory (2LM), where a first level memory acts as a cache for the second level memory. A memory controller or cache controller can detect a cache miss in the first level memory for a request for data. Instead of automatically performing a swap, the controller can determine whether to perform a swap based on a swap policy assigned to a memory region associated with the address of the requested data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.