Controlling memory frequency based on transaction queue occupancy
US12386749B2 · kind B2 · utility
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3References
19Claims
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Key dates
| Filing date | Nov 18, 2020 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Dec 2, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques and apparatuses are described that use transaction queue lengths to alter a clock frequency that controls access to a memory of an electronic device. Techniques include detecting that a transaction queue threshold has been violated, initiating a counter to measure a time duration, determining that the transaction queue threshold continues to be violated for the time duration and, in response, altering the clock frequency that controls access to the memory of the electronic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.