Patent · US Active

Interconnect for direct memory access controllers

US12386766B2 · kind B2 · utility

0Cited by

4References

20Claims

0Family size

Assignee

MICROSOFT TECHNOLOGY LICENSING, LLC · US

Inventors

Ruihua Peng · Santa Clara, US
Monica Man Kay Tang · Santa Clara, US
Xiaoling Xu · Beijing, CN

Key dates

Filing date	Apr 12, 2024
Grant date	Aug 12, 2025
Priority date	—
Expiry date	Apr 12, 2044

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A computing device is provided, including a plurality of memory devices, a plurality of direct memory access (DMA) controllers, and an on-chip interconnect. The on-chip interconnect may be configured to implement control logic to convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device of the plurality of memory devices. The on-chip interconnect may be further configured to implement the control logic to convey a read response from the source memory device to the primary DMA controller and one or more secondary DMA controllers of the plurality of DMA controllers.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.