Chip power consumption analyzer and analyzing method thereof
US12387023B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 1, 2022 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Apr 28, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are a chip power consumption analyzer and an analyzation method thereof. The analyzation method includes the following. Design information of a circuit is received. A plurality of clock arriving times of a plurality of circuit cells in the circuit are calculated based on the design information, and a base cell type is set among a plurality of cell types according to the clock arriving times. Base demand current information of the base cell type is established, and a plurality of demand current information of the circuit cells is obtained. A plurality of demand peak currents of a plurality of bump current sources are predicted according to the demand current information and a plurality of position information of the circuit cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.