System, method, computer-accessible medium, and circuit for crippling the oracle in logic locking
US12387024B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 7, 2021 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | May 25, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Exemplary system, method, and computer-accessible medium for protecting at least one logic-locked integrated circuit (IC) design can include, for example, receiving a request(s), and swapping a correct key which is configured to unlock the logic-locked IC design(s) with an incorrect key which is configured to corrupt an output(s) of the logic-locked IC design(s) after receipt of the request(s). The request(s) can be a test access request(s). The correct key can be utilized when the logic-locked IC design(s) can be initially powered on. The correct key can be swapped with the incorrect key using multiplexer(s) or register(s). In addition, exemplary system, method, and computer-accessible medium can be provided for logic-locking a logic design by, randomly replacing randomly-selected inverters in the logic design with XOR or XNOR key-gates, and inserting XOR or XNOR key-gates randomly in randomly-selected locations in the logic design where there is no inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.